Funding (Industry - R& D)

• Co-PI for industrial R & D project with Prof. Sachit Rao for Aditya AvartanTechnologies (completed).

• Consultant (R&D) for a UK based company for FPGA implementations (completed).

Chip Tape-outs

• Tapeout-1: Skywater 130nm – Scalable LFSR Driven Lightweight Cryptography (In Fab)

• Tapeout-2: SCL 180nm – NIST Ratified Crypto Engine for Edge Devices (In-Progress)

• Tapeout-3: SkyWater 130nm – Accelerator for light Machine Learning Workloads (In-Progress).

• Tapeout-4: TSMC 65nm – Quantum Cryptography Engine – Edge Devices (In-Progress)

Silicon Proven FPGA - IPs

• FPGA IP-1: Avnet Ultra96v2 - Fully Convolutional Network for Leaf Disease Detection.

• FPGA IP-2: Avnet Ultra96v2 - Simple Reinforcement Learning on Edge-Devices.

• FPGA IP-3: Xilinx ZCU104 - Accelerating Activation Function Selection for DNNs.

• FPGA IP-4: Xilinx ZCU104 - Resource Constrained Neural Network Training.

• FPGA IP-5: Xilinx ZCU104 - Edge LLM for Genome sequencing using Ecoli - Dataset.

• FPGA IP-6: Xilinx ZCU104 - Multi Agent Deep Reinforcement Learning for Edge Devices.

Technical Skills/Grant Writing

• R & D Proposals:

  • Contributor for Proposal submitted to Ministry of Telecommunication, Govt of India (Prof. S K Roy)

  • Contributor for Proposal submitted to Industry (NXP) (Prof. Sachit Rao and Prof. S K Roy)

•  Hardware Boards: Avnet Ultra96v2 FPGA, Xilinx ZCU104 FPGA, Google-Coral Edge TPU

•  Digital Design: Verilog HDL; High Level Synthesis (HLS); RTL Design-Descriptions/Abstraction

•  Hardware Verification: System Verilog; Universal Verification Methodology (UVM)

•  Programming Languages: C, C++, Python; Protocol: AMBA – AXI, UART, SPI

•  Operating Systems: Linux-Red Hat, Microsoft Windows (XP/07/08/10)

• Software/ Tools: Xilinx - Vitis, PYNQ, SDK, HLS, Vivado, MATLAB, Cadence (Genus), Mentor Graphics (Modelsim/Questasim), MS-Office (Word, Excel, Power point, Outlook)

• Others: TensorFlow, PyTorch, Keras

Certification/Workshops

• DST - GDC I-NCUBATE - Entrepreneur Workshop – IIT Madras (May to July 2025).

• Telecommunication Standardization Awareness Workshop, Dept. of Telecommunications, GoI.

• Matlab – Deep Learning, Machine Learning, Reinforcement Learning, Simulink.

• Xilinx (CoreEL) – Vivado, Vitis, ZynQ.

• Mentor Graphics – Semi Custom and Full Custom.

• Cadence (DAC Summer School) – High Level Synthesis.

• IBM-MeitY-IIT Guwahati - Open Power ISA RISC based Architecture Design.

• Global Semiconductor Innovation-Chinese American Semiconductor Professional Association (CASPA).

• CHIPS Alliance Fall Workshop.

• Telluride Neuromorphic Cognition Engineering Workshop.

• NVIDIA GTC- 2021.