Patents

  1. Method and System for Multi-Sensor Data Processing (Published IPO Application No: 202541061206 A).

  2. Hardware accelerator for Transformer Computation - Edge Devices (Pending).

  3. Crypto Engine for Quantum Safe Computing (Pending).

Book

Subir K Roy and S. M. Waseem, “Embedded Systems Design”, Cambridge University Press – In progress.

Book Chapter

  1. S. M. Waseem and Subir K Roy, “Fully Convolutional Network for Edge devices - FPGA implementation and Analysis for Agriculture Technology” in Agri 4.0 and the Future of Cyber-Physical Agricultural Systems, Elsevier, Netherlands, 2024, DOI: 10.1016/B978-0-443-13185-1.00010-1.

  2. S. M. Waseem and Subir K Roy, “Heterogeneous Computing of Multi Agent Deep Reinforcement Learning on Edge Devices for Internet of Things” in Heterogeneous Computational Intelligence in Internet of Things, CRC Press, Taylor and Francis Group, USA, 2023, DOI: 10.1201/9781003363606-2.

  3. S. M. Waseem and Subir K Roy, “Hardware Realization of Reinforcement Learning Algorithms for Edge Devices” in VLSI and Hardware Implementations using Modern Machine Learning Methods, CRC Press, Taylor and Francis Group, Boca Raton, USA, 2021, DOI: 10.1201/9781003201038-12.

Journal

  1. S. M. Waseem, I. Batterywala, S. K. Roy and S. Rao “ Robotic Navigation with the help of INR”, (Under Review).

  2. S. M. Waseem and Subir K Roy, “FPGA implementation of Proximal Policy Optimization Algorithm for Edge Devices with application to Agricultural Technology”, Journal of Ambient Intelligence and Humanized Computing, Springer, 2022, DOI: 10.1007/s12652-022-04117-z.

  3. S. M. Waseem and A. Fatima, “Power optimized 7-port router design with BIST capability for 3D NoC architecture” Journal of Electrical and Electronics Engineering, University of Oradea, Romania, 2017.

Conference

  1. S. M. Waseem, I. Batterywala, S. K. Roy and S. Rao, "FPGA Based Hardware Accelerator for Training Implicit Neural Representations on Edge Devices," 2024 12th International Conference on Intelligent Systems and Embedded Design (ISED), NIT Rourkela, India, 2024, pp. 1-6, doi: 10.1109/ISED63599.2024.10957434.

  2. S. M. Waseem, I. Batterywala, S. K. Roy and S. Rao, "FPGA Implementation and Analysis of Non-Linear Activation Functions for Implicit Neural Representations," 2024 IEEE Region 10 Symposium (TENSYMP), New Delhi, India, 2024, pp. 1-7, doi: 10.1109/TENSYMP61132.2024.10752188.

  3. A. V. Suraj, S. M. Waseem and S. K. Roy, "Resource Constrained Hardware Architecture for Training Deep Neural Networks at the Edge - FPGA Implementation," 2022 IEEE International Symposium on Smart Electronic Systems (iSES), NIT Warangal, India, 2022, DOI: 10.1109/iSES54909.2022.00079.

  4. S. M. Waseem, A. V Suraj and S. K. Roy, "Accelerating the Activation Function Selection for Hybrid Deep Neural Networks – FPGA Implementation," 2021 IEEE Region 10 Symposium (TENSYMP), Jeju, Republic of Korea, 2021, DOI: 10.1109/TENSYMP52854.2021.9551000.

  5. S. M. Waseem and A. Fatima, “Cellular Automata and Arbiter PUF-Based Security Architecture for System-on-Chip Designs”, 2019, Lecture Notes in Electrical Engineering, vol 521. Springer, Singapore. DOI: 10.1007/978-981-13-1906-8_28.

  6. S. M. Waseem and A. Fatima, “Cellular Automata Logic Block Observer Based Testing for Network-on- Chip Architecture”, Advances in Intelligent Systems and Computing, vol 673. Springer, Singapore.https://doi.org/10.1007/978-981-10-7245-1_3.

  7. S. M. Waseem and A. Fatima, "Test scheduling with built in logic block observer for NoC architecture", 2017 IEEE International Conference on Innovative Mechanisms for Industry Applications (ICIMIA), Bengaluru, India, 2017, DOI: 10.1109/ICIMIA.2017.7975601.

  8. A. Fatima and S. M. Waseem, "Cellular Automata based Built-In-Self Test implementation for Star Topology NoC," 2017 IEEE 11th International Conference on Intelligent Systems and Control (ISCO), Coimbatore, India, 2017, DOI: 10.1109/ISCO.2017.7856039.

  9. S. M. Waseem and A. Fatima, "Pursuance measures of CRA & HRA for 3D networks on a 7-port router schema," 2015 IEEE International Conference on Communications and Signal Processing (ICCSP), India, 2015, DOI: 10.1109/ICCSP.2015.7322547.

Poster

S. M. Waseem, S. K. Roy, “Simple Reinforcement Learning for Edge Devices-FPGA Implementation”, 58th Design Automation Conference, (DAC), ACM/IEEE, DACYF, 2021, San Francisco, USA.

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