Education
Ph.D (AI/ML - VLSI & Embedded Systems) – IIIT Bangalore (India) – 2019 to 2023 (3.77/4.00)
M.Tech (VLSI) – JNTUH (India) – 2012 to 2014 (84%)
B.E (ECE) – Osmania University (India) – 2008 to 2012 (79%)
XII – BIE (India) – 2006 -2008 (96%)
X – SSC (India) – 2006 (88%)
Work Experience
Senior Researcher and CTO – EdgeRON Technologies Pvt Ltd (incubated at IIITB) – Oct 2024 to Till date
I have been active in building entire technical portfolio of the company besides engaging with customers and companies for B2B segment- product/market portfolio. I have participated in several CXO level talks along with other co-founders, in my journey so far in customer discovery, fund raising and Venture Capitalists discussions.
Post-Doctoral Fellow – Robotic Studio - MINRO – IIIT Bangalore (IN) – Sep 2024 to Dec 2025
Funder: Karnataka Innovation & Technology Society, Dept. of IT, BT and S&T, Govt. of Karnataka
Area: Hardware for ML/RL, CNN, FPGA, VLSI and Embedded Systems
Other: Research Grant Proposal Writing, Leading Team of 5-Researchers, collaborating with Industry/
Academia/Govt. Agencies for Grants and Approvals, Teaching Assistant for UG/PG courses related to VLSI and
Embedded Systems
Research Associate (Post-Doctoral) – MINRO – IIIT Bangalore (IN) – Sep 2023 to Aug 2024
Funder: Karnataka Innovation & Technology Society, Dept. of IT, BT and S&T, Govt. of Karnataka
Area: Hardware for ML/RL, CNN, FPGA, VLSI and Embedded Systems
Other: Research Grant Proposal Writing, Leading Team of 5-Researchers, Collaborating with Industry/
Academia/ Govt. Agencies for Grants and Approvals, Teaching Assistant for UG/PG courses related to VLSI and
Embedded Systems
Research Scholar – IIIT Bangalore (IN) – July 2019 to August 2023
Funder: Machine Intelligence and Robotics Centre, IIIT Bangalore
Area: Hardware for ML/RL, FPGA, VLSI and Embedded Systems
Teaching Assistant – 1) Signals and Systems (Undergraduate Course)
2) Design For Testability (Postgraduate Course)
Research Fellow – University Malaysia Perlis (UniMAP) (MY) – Oct 2018 to June 2019
Product Manager – IF&S, IN – Oct 2016 to June 2019
Technical Manager – Networking & Communications – SMR Industries, IN Aug 2015-Sep 2016
Senior Technical Engineer – Avaya Inc – Hyderabad (IN) – Feb 2014 to Aug 2015
Research Intern – IIIT Hyderabad (IN) – Oct 2011 to Apr 2012 & Nov 2013 to Jan 2014
Subjects Experience at IIIT Bangalore
ESS103 Signals and Systems (Teaching Assistant)
VL601 Testing and Design for Testability (Teaching Assistant)
Digital Chip Design using Verilog HDL (Karnataka VLSI Program)
Other Subjects of Interest
System on Chip (SoC) design - Field Programmable Gate Arrays
Machine Learning – Mathematics and Hardware Architectures
Autonomous Control – Reinforcement Learning
HDL and High-Level Synthesis
Digital Integrated Circuit Design
VLSI Digital Signal Processing Systems
Computer Architecture